The present invention relates to a method for manufacturing a semiconductor device utilizing overhangs to block ion implantation of the bottom of deep and wide trenches at the device edge terminations, enhancing the voltage blocking capability of the device terminations. The overhangs are created by non-comformally depositing thick oxide to seal the top of each trench in a selected area, thereby allowing the deposition of photoresist, nitride or polysilicon to form the overhangs without the material going into the trenches. The resulting semiconductor device is a metal-oxide semiconductor (MOS)-gated power device suitable for power switching, having both a low on-resistance RON and a high breakdown voltage Vb.
Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.
U.S. Pat. No. 6,410,958 (“Usui, et al.”) relates to an edge termination structure and a drift region for a semiconductor component. A semiconductor body of the one conductivity type has an edge area with a plurality of regions of the other conductivity type embedded in at least two mutually different planes. Underneath the active zone of the semiconductor component, the drift regions are connected using the underlying substrate.
U.S. Pat. No. 6,307,246 (“Nitta, et al.”) discloses a semiconductor component having a high-voltage sustaining edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. During commutation of the power semiconductor component, the shaded source zone regions suppress the switching “on” of a parasitic bipolar transistor caused by the disproportionately large reverse flow current density. Moreover, an edge structure having shaded source zone regions can be produced very easily in technological terms that are discussed in the Nitta, et al patent. It clarifies the effects of parameters and enables the mass production of a superjunction semiconductor device which has a drift layer composed of a parallel PN layer that conducts electricity in the “on” state and is depleted in the “off” state. The net quantity of active impurities in the N-type drift regions is within the range of 100% to 150% of the net quantity of active impurities in the P-type partition regions. In addition, the width of either one of the N-type drift regions and the P-type partition regions is within the range between 94% and 106% of the width of the other regions.
U.S. Pat. No. 6,300,171 (“Frisina”) discloses a method for manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers. The second step up to the sixth step are repeated at least one time in order to form a final edge structure including a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers and formed by superimposition of the doped regions subsequently implanted through the mask openings, the columns near the high voltage semiconductor device being deeper than the columns farther from the high voltage semiconductor device.
It is desirable to provide a semiconductor device with an enhanced voltage blocking edge termination, in which the bottom of the deep and wide trench at the termination is not ion implanted, and includes a thick oxide region. It is also desirable to provide such a device that is manufactured using a technique compatible with a process using only a single epitaxial deposition step in the manufacture of the device.